With the continuous development of semiconductor technology and the continuous decreasing of the process node, gate-last technology has been widely used to obtain a desired threshold voltage and an improved device performance. However, when the critical dimension (CD) of the device further decreases, even with the gate-last process, the conventional MOS field effect transistor structure is unable to meet the demand of the device performance. Therefore, multi-gate devices, as an alternative to the conventional devices, have been widely considered.
A fin field effect transistor (Fin FET) is a common multiple gate device. FIG. 1 shows a perspective schematic structural diagram of an existing fin FET. As illustrated, an existing fin FET can comprises: a semiconductor substrate 10, a fin portion 14, a dielectric layer 11, and a gate structure 12. The fin portion 14 is projected on the semiconductor substrate 10. The fin portion 14 is generally formed by etching the semiconductor substrate 10. The dielectric layer 11 covers the surface of the semiconductor substrate 10 and a portion of the sidewalls of the fin portion 14. The gate structure 12 is disposed astride the fin portion 14 to cover the top and sidewalls of the fin portion 14. The gate structure 12 comprises a gate dielectric layer (not shown in FIG. 1) and a gate electrode layer (not shown in FIG. 1) located on the gate dielectric layer. For the existing fin FET, the top portion and the sidewalls of the fin portion that contact with the gate structure 12 are channel regions. That is, the existing fin FET can have multiple gates which are conducive to increase the drive current and to improve the device performance.
However, with further size decreasing of the process node, the performance of the semiconductor devices that contain the above-described existing fin FET remains problematic. The disclosed semiconductor device and fabrication method are directed to solve one or more problems set forth above and other problems